Recently, the development of the miniaturization and high-density mounting of electronic parts used for electronic equipment has been carried out to respond to requests for multifunction capability, miniaturization and reduction in weight of electronic equipment such as personal computers and picture acoustic equipment. Especially, the design rule of semiconductor apparatus such as LSI has been hyperfined, the wiring pitch of the printed wiring substrate used for mounting the electronic parts with high density has been reduced to a minimum and multilayered wiring is formed on the printed circuit board.
The density of multilayered device such as multilayered printed wiring substrates and MCM multilayered substrate or devices on which multilayered structure wiring is formed such as LSI has been increased, so the demand has grown for a wiring pattern having a fine structure. On the other hand, it is also required for the device to be manufactured at low cost. It is very difficult to solve both the above-mentioned problems at the same time. One of the solutions concerning the production technique is such that the device is manufactured on a large scale. For example, in manufacturing multilayered printed circuit boards, it is very effective to manufacture a large number of printed circuit boards at a time by using one piece of large scale substrate, in the so-called multi-production technique, to reduce the production cost for each piece of the printed circuit board. In order to achieve the above-mentioned effect, in the printed circuit board industry, a process is employed in which a large scale square substrate having a side of about 500 mm is used to manufacture a large number of printed circuit boards. In addition to that, in the semiconductor substrate industry, a process in which a large number of LSI are formed on an 8-inch silicon wafer is employed. Taking advantage of high level heat-resistance, the change in size due to shrinkage caused by firing of the ceramic multilayered substrate used for electronic controller such as automobile is large, therefore, in general, a square ceramic multilayered substrate having a length about 100 to 300 mm, which is smaller than that of printed circuit board, is used.
Hereinafter, a conventional method of forming multilayered pattern such as the above-mentioned printed circuit board will be explained. FIGS. 5A-5F show a process for forming a multilayered printed circuit board by a conventional manufacturing method. This conventional method of manufacturing a printed circuit board comprises the following steps:
(a) coating photosensitive insulating layer 505 on a top surface of glass epoxy multilayered wiring board 504 comprising an inside wiring pattern 501, a top surface wiring pattern 502 and a bottom surface wiring pattern 503 (as shown in FIG. 5A); PA1 (b) locating a first mask 506 on which a pattern is formed to form a via hole to fit the top surface wiring pattern 502 formed on the insulating layer 505 (as shown in FIG. 5B); PA1 (c) removing the insulating layer 505 at the position of a via hole to be punched by exposing over the first mask 506 by photolithography to form a via hole 507 (as shown in FIG. 5C); PA1 (d) activating the inside wall of the via hole 507 with Sn-Pd to give conductivity and plating Cu to form a conductive layer 508 on the whole surface of the inside wall of the via hole 7 (as shown in FIG. 5D); PA1 (e) locating a second mask having a pre-designed wiring pattern on the conductive layer 508 (as shown in FIG. 5E); and PA1 (f) exposing by the photolithography or etching to form a wiring pattern 510 to be achieved(as shown in FIG. 5F). PA1 (a) forming a bottom side wiring pattern of an aluminum deposited film or sputtered film on a top surface of silicon wafer on which an active element or a passive element is formed; PA1 (b) covering the bottom side wiring pattern with a dielectric layer composed of silicon oxide and forming a via hole by photolithography; PA1 (c) forming a conductive layer by sputtering or depositing; and PA1 (d) forming a top side wiring pattern by photolithography in the same way. In the above-mentioned process of forming a wiring pattern of an LSI, the accurate positioning of the mask is required when photolithography is employed in the same way as that of the method of manufacturing a printed circuit board. Further, a passive element and an active element are manufactured by repeating photolithography a plurality of times. PA1 forming a first wiring pattern having a predetermined configuration composing a first conductive layer on a surface of a supporting substrate composed of insulating material; PA1 recognizing a position and a configuration of the first wiring pattern by recognizing means; PA1 covering a top surface of the first wiring pattern with an insulating layer; PA1 providing a via hole on a top surface of the insulating layer at a predetermined position by boring means adjusting to the position and the configuration of the first wiring pattern based on a picture signal detected by the recognizing means; PA1 providing conductive material in the via hole and forming a second conductive layer on the whole surface of the insulating layer; PA1 forming a photoresist film on the top surface of the second conductive layer, and plotting and sensitizing a second wiring pattern having a predetermined configuration on the photoresist layer based on a picture signal detected by the recognizing means; PA1 etching a second conductive layer via a sensitized and developed photoresist and removing the photoresist to form a second wiring pattern; and PA1 connecting electrically the first wiring pattern and the second wiring pattern through a via hole on which the insulating layer is provided to form a multilayered wiring board. PA1 forming a first wiring pattern having a predetermined configuration composed of a first conductive layer on a surface of a supporting substrate composed of an insulating material; PA1 recognizing a position and a configuration of the first wiring pattern by recognizing means and bonding a second conductive layer composed of copper foil via an insulating adhesive resin layer on the surface of the first wiring pattern; PA1 forming a photoresist layer on the surface of the second conductive layer and plotting and sensitizing a pattern of a via hole or holes in the photoresist layer at predetermined positions based on a picture signal of the configuration and the position of the first wiring pattern detected by the recognizing means; PA1 forming an opening part for boring a via hole or holes in the second conductive layer by etching the second conductive layer via mask composed of the sensitized and developed photoresist; PA1 forming a via hole or holes by boring means in a resin layer in the opening part; PA1 plating copper in the via holes and on the whole surface of the second conductive layer; and PA1 forming a second wiring pattern by using plotting means to adjust the position and the configuration of the first wiring pattern based on a picture signal detected by recognizing means. As above-mentioned, this preferred embodiment employs simplified steps, so that a multilayered wiring board with high reliability can be manufactured at lower cost. PA1 recognizing a pattern on a multilayered substrate comprising a ceramic as an insulating layer and a plurality of layers of a conductive pattern formed therein by recognizing means and storing the information; PA1 forming a conductive layer on a surface of the multilayered substrate; PA1 coating a photoresist on a whole surface of the conductive layer; PA1 plotting a pattern, which is formed by calculation based on the information stored by recognizing means, on the photoresist; and PA1 removing the photoresist selectively, dissolving and removing unnecessary parts of the conductive layer by etching to form a multilayered wiring board. PA1 recognizing by recognizing means a position and a configuration of at least one of a plurality of patterns which were already formed; and PA1 forming a succeeding diffusion pattern, a succeeding contact window or a succeeding wiring pattern by plotting means or by photolitho technique adjusting to the recognized pattern to manufacture a semiconductor equipment. Accordingly, an LSI chip excellent in reliability can be manufactured using a large scale of work substrate (silicon wafer) with high efficiency. PA1 recognizing by recognizing means a position and a configuration of at least one of a plurality of patterns which were already formed; and PA1 forming a succeeding pattern or a succeeding wiring pattern by plotting means or by a photolitho technique adjusting to the recognized pattern to manufacture a liquid crystal display equipment.
A basic method of manufacturing a semiconductor device such as an LSI device is the same as that of the above-mentioned method of manufacturing a printed circuit board. The method of manufacturing a semiconductor device comprises the following steps:
As above-mentioned, the number of electronic parts per one piece of work substrate (one piece of unit substrate on which a large number of electronic parts are multi-produced at the same time, for example, an 8-inch silicon wafer for LSI) has to be increased in order to reduce the production cost of the electronic parts of the printed circuit board or LSI. However, in the above-mentioned conventional method of forming a wiring pattern, the size of the work substrate becomes bigger, and accuracy of positioning becomes lower. In addition to that, the coefficient of thermal expansion of the mask, the substrate material and the conductive layer used in the conventional method of forming are different, therefore a difference of size is caused and consequently the yield is lowered. For example, a printed circuit board comprising glass epoxy as substrate comprises inorganic glass fiber and organic epoxy resin in the substrate and a wiring pattern composed of metallic material is formed thereon. Accordingly, in general, the thermal expansions of the materials composing the printed circuit board are different and during the manufacturing process, the material is stressed by applying pressure and heat. Therefore it is very difficult for photolithography to improve the size accuracy which a plurality of material is layered and mask is aligned. Further, as the number of layers in the wiring patterns increases, the difficulty of improving the size accuracy increases accordingly.
FIG. 6 shows an example of a work board for multi-production employed in a general method of forming a wiring pattern. As shown in FIG. 6, twenty five pieces of printed circuit boards 602 on which a wiring pattern 604 and a via hole 605 are formed are formed by using work board 601. Element 603 indicates a reference bore which is used to maintain the accuracy of the size in aligning the mask when photolithography is employed. As shown in FIG. 7, due to the change of size caused by thermal expansion, some parts of via hole 605 for connecting a wiring pattern 604 of the surface layer with a wiring pattern 701 of the under layer can not be accurately positioned. When some part of via hole 605 deviates as indicated by 605a, the electrical connection becomes unstable, and the reliability of the manufactured product is lowered. Further, when the position of the via hole deviates entirely, as indicated by 605b, the manufactured product becomes inferior, and production yield is lowered.
In general, when a square work board having 500 mm side is used, it is difficult to make a size error in positioning of 100 .mu.m or smaller. As mentioned above, when the density of wiring pattern becomes higher, the difficulty of reducing size error in positioning increases.
This invention provides a method of forming multilayered wiring patterns in which respective wiring patterns can be formed with high accuracy without being affected by the change of size caused by difference of coefficient of thermal expansion of the respective materials even if the size of work board becomes large to reduce production cost. This invention also provides a method of forming multilayered wiring patterns in which a plurality of wiring patterns formed for a multilayer circuit can be connected accurately with via holes, so that production yield can be improved and electronic parts excellent in reliability can be produced at low cost.